1. Field of the Invention
The present invention relates to a computer system, and more particularly, to a error sensing and correction apparatus within said computer system for automatically sensing the existence of an error within said computer system, for correcting said error, and for automatically ensuring that said error will never again re-occur.
2. Description of the Prior Art
A memory often includes a plurality of integrated circuit chips. The integrated circuit chips each include a plurality of cells. If one or more cells of an integrated circuit chip in the memory fail, the binary data, stored in the cells, is erroneously changed. When the data is read from the memory, the erroneous binary data is included as part of the data read from memory.
Various schemes have been devised to detect the existence of the erroneous data, to correct the data, and to take steps to ensure that the corrected data will be retrieved from memory when the memory is subsequently addressed. For example, U.S. Pat. No. 3,222,653 to Rice and IBM technical disclosure bulletin Vol. 12, No. 9, February 1970, pages 1441 through 1444 disclose such schemes. In U.S. Pat. No. 3,222,653, if data, withdrawn from a defective location in memory, is determined to be erroneous, the data is corrected and stored in an auxiliary location of the memory. The address of the auxiliary memory location may be stored in a non-defective portion of the defective location in memory wherein the data was originally stored. However, if the defective location in memory, wherein the data was originally stored, is completely defective, the address of the auxiliary memory location and the corresponding address of the defective location in memory are stored in one register in a special section of memory. During a subsequent read of the data stored in the defective location in memory, the integrity of the data must first be checked. An error indicator indicates that the data stored in the defective location in memory is not a data word. The data stored in the defective location in memory may then be interpreted as being the address of the auxiliary memory location wherein the data is actually stored. The auxiliary memory location is addressed at a location corresponding to the data stored in the defective location in memory. As a result, the corrected data is read from the auxiliary location in memory. If the location in memory is completely defective, when the error indicator has indicated that the data stored in the defective location is not a data word, the address of the defective location must be found in the one register of the special section of memory. When the address is found, the address of the auxiliary location in memory is noted. The corrected data is then retrieved from the auxiliary location in memory. A similar functioning occurs with respect to the apparatus disclosed in the above referenced technical disclosure bulletin.
In the patent and the technical disclosure bulletin, during the subsequent read of the data stored in the defective location in memory, the memory must be read twice in order to retrieve the corrected data, a first read being in the defective location, a second read being in the auxiliary location in memory. Since the memory must be read twice, performance problems may occur with respect to the functional operation of the computer system. Furthermore, if the location in memory is completely defective, the memory must be read three times, a first being in the defective location in memory, a second being in the one register of the special section in memory to locate the address of the auxiliary memory location, and a third being in the auxiliary memory location. This may create a performance problem. In addition, in the patent, a read cycle must precede a write cycle in order to determine whether the location in memory, wherein the data is to be stored, is defective. Further performance problems can result from this requirement.
It is noted that the address of the auxiliary memory location, wherein the corrected data is stored, resides in the same memory as that in which the data was originally stored, that is, either in the defective location or in the special section of the memory. As a result, the memory must be read twice or three times to retrieve the corrected data.
A number of additional prior art publications exist.
1. IBM Technical Disclosure Bulletin, "Automatic Repair Method", J. P. Roth, Vol. 10, No. 7, December 1967, pp. 915-916.
2. IBM Technical Disclosure Bulletin, "Allocation of Redundant Memory Components", F. J. Aichelmann, Jr. and L. K. Lange, Vol. 24, No. 9, February 1982, pp. 4776-4778.
3. IBM Technical Disclosure Bulletin, "Effective Scheme for Utilizing Partially Good Chips in Memory System", G. G-C. Liu, Vol. 20, No. 8, January 1978, pp. 3009-3010.
4. IBM Technical Disclosure Bulletin, "Storage Module Reconfiguration to Bypass Bit Failures", W. G. Bouricius, W. C. Carter, J. P. Roth and P. R. Schneider, Vol. 11, No. 5, October 1968, pp. 550-551.
5. IBM Technical Disclosure Bulletin, "Processing System", R. P. Fletcher, Vol. 11, No. 5, October 1968, p. 515.
6. IBM Technical Disclosure Bulletin, "Error Correction by Reconfiguring", J. E. Heasley, Jr. and R. F. McMahon, Vol. 10, No. 10, March 1968, pp. 1543-1544.
7. IBM Technical Disclosure Bulletin, "Logical Deletion of Portions of a Push-Down Algorithm", E. L. Allen, Jr., V. L. Blunk, E. J. Ossolinski and H. G. Weber III, Vol. 12, No. 12, May 1970, pp. 2150-2151.
8. IBM Technical Disclosure Bulletin, "Removal of Failing Buffer sections in a Buffer-Backing Store". M. W. Bee, W. E. Boehner, J. L. Burk and B. L. McGilvray, Vol. 13, No. 2, July 1970, pp. 400-402.